Fir filter,method of operating the same, semiconductor integrated circuit including fir filter, and communication system for transmiting data filtered by fir filter

ABSTRACT

The FIR filter separately receives input data consisting of transmitting information and composed of bit strings, and additional data which is added in order to transmit the input data. The input data is operated with the additional data. A difference between the additional data corresponding to previous data (for instance, most recent data) among the input data and the additional data corresponding present data is obtained, and the difference and the previous data are operated. Then, the operation results are added and the resultant is outputted as a filter response. The input data and the additional data are separately received to be operated so that the circuit scale of the filter is reduced. Therefore, a chip of the semiconductor integrated circuit can be downsized and thereby cost reduction in the communication system can be realized.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to an FIR filter to be used inportable terminals or the like in mobile communication systems.

[0003] 2. Description of the Related Art

[0004] Since an FIR (Finete Impulse Response) filter has liner phasecharacteristics, a transfer function, and stability which cannot berealized by an analog filter, it is utilized for various usages such ascommunication systems and audio apparatuses. For example, the FIR filteris applied to a filter in a CDMA (Code Division Multiple Access) systemand so on, which is one of digital mobile communication systems. In theCDMA system, a transmission rate is variable so an input resolving powerenough to express a ratio of change amounts in transmission rate isnecessary. Therefore, the resolving power (a bit width) of input data toa filter is required to be increased as a transmission rate increases. Aresolving power for obtaining a sufficient distance between signalpoints is also required for a code-multiplexed transmission of the CDMAsystem.

[0005] Generally, the FIR filter is composed of a shift register, amultiplier, an adder, and so on. These circuits need to be constitutedto correspond to the maximum resolving power of input data. As a result,the circuit scale of the filter is enlarged according to a bit width ofthe input data. The circuit scale of the multiplier is in particularenlarged to a large extent according to an increase in bit width of theinput data. However, the above-mentioned input resolving power does notvary all the time. In general, an interval at which the transmissionrate changes is sufficiently longer than a time needed for the inputdata to pass through the shift register.

SUMMARY OF THE INVENTION

[0006] It is an object of the present invention to shorten a bit widthof input data to an FIR filter and to reduce a hardware scale.

[0007] According to one of the aspects of an FIR filter, a method ofoperating the FIR filter, a semiconductor integrated circuit includingthe FIR filter, and a communication system for transmitting datafiltered by the FIR filter of the present invention, the FIR filterseparately receives input data consisting of transmitting informationand composed of bit strings, and additional data which is added in orderto transmit the input data. The input data is operated with theadditional data. The operation is performed, for example, in a firstoperational unit. A difference between the additional data correspondingto previous data (for instance, most recent data) among the input dataand the additional data corresponding present data is obtained, and thedifference and the previous data are operated. The operation isperformed, for instance, in a second operational unit. Then, theoperation results are added, for example, in an adding unit and theresultant is outputted as a filter response.

[0008] The input data and the additional data are separately received tobe operated so that the circuit scale of the filter is reduced comparedwith a case where data which is input data and additional data combinedand has a large bit width, is received. Therefore, a chip of thesemiconductor integrated circuit can be downsized and thereby costreduction in the communication system can be realized.

[0009] According to another aspect of the FIR filter of the presentinvention, the FIR filter includes a shift register and factormultipliers. The shift register receives input data in sequence andtransmits the received input data to respective delay elements. Each ofthe factor multipliers multiplies an output from each of the delayelements of the shift register by tap factors. The first operationalunit includes a first adder tree and a first multiplier. The first addertree adds outputs from the factor multipliers. The first multipliermultiplies an output from the first adder tree by the additional data.The second operational unit includes a second adder tree and a secondmultiplier. The second adder tree adds an output corresponding to theprevious data from the factor multipliers. The second multipliermultiplies an output from the second adder tree by a difference in theadditional data. The adding unit adds an output from the firstmultiplier and an output from the second multiplier to output theaddition result as a filter response.

[0010] A reduction in bit width of input data realizes a decrease in thenumber of the factor multipliers and further realizes a reduction in thecircuit scales of the first and second adder trees and the first andsecond multipliers.

[0011] According to another aspect of the FIR filter of the presentinvention, the FIR filter includes switches for respectively connectingoutputs of the factor multipliers to the second adder tree. The switchesare switched on and off in response to a shift operation performed onthe input data in the shift register. Then, the previous data among datasequentially held in the delay elements is transmitted to the secondadder tree.

[0012] According to another aspect of the FIR filter and the method ofoperating the FIR filter of the present invention, the FIR filtersequentially receives input data consisting of transmitting informationand composed of bit strings. Present data among the input data isoperated with additional data which is added in order to transmit thepresent data. The operation is performed, for example, in the firstoperational unit. Previous data among the input data is operated withthe additional data corresponding to the previous data. The operation isperformed, for example, in the second operational unit. Then, theoperation results are added, for instance, in the adding unit and theresultant is outputted as a filter response. The input data and theadditional data are separately received to be operated so that thecircuit scale of the filter is reduced.

[0013] According to another aspect of the FIR filter and the method ofoperating the FIR filter of the present invention, the filtersequentially receives input data consisting of transmitting informationand composed of bit strings. Present data among the input data is added.The operation is performed, for example, in the first operational unit.A ratio of the additional data corresponding to previous data among theinput data to the additional data corresponding to the present data isobtained, and the ratio and the previous data are operated. Theoperation is performed, for instance, in the second operational unit.The operation results are added, for example, in the adding unit. Theaddition result is multiplied by the additional data corresponding tothe present data. The multiplication is performed, for example, in amultiplying unit. The multiplication result is outputted as a filterresponse. The input data and the additional data are separately receivedto be operated so that the circuit scale of the filter is reduced.

[0014] According to another aspect of the FIR filter of the presentinvention, the FIR filter includes a data separation unit for separatingdata which is inputted to the filter and composed of bit strings, intothe input data and the additional data. Thereby, the data which is theinput data and the additional data combined can be easily separated.

[0015] According to another aspect of the FIR filter of the presentinvention, the switches are switched off in response to every shiftoperation of the shift register. The switching-off is sequentiallyperformed, starting from a switch corresponding to one of the factormultipliers at an input side. Therefore, only previous transmitted data,among data transmitted in sequence to each of the delay elements on asubsequent stage in response to the shift operation, is reliablytransmitted to the second adder tree.

[0016] According to another aspect of the FIR filter of the presentinvention, the FIR filter includes a switch for connecting an output ofa predetermined factor multiplier to the second adder tree and a switchfor connecting an output of a predetermined adder which is included inadders composing the first adder tree, to the second adder tree. Each ofthe switches is switched on and off in response to a shift operation ofthe input data in the shift register and transmits previous data to thesecond adder tree. The addition result from the adders in the firstadder tree can be utilized so that the circuit scale of the second addertree is reduced.

[0017] According to another aspect of the FIR filter of the presentinvention, the FIR filter includes a holding circuit and an operationalcircuit. The holding circuit accepts the additional data in response toa change in input data and holds the accepted data as the additionaldata corresponding to previous data. The operational circuit obtains adifference between the additional data outputted from the holdingcircuit and new additional data. Thereby, the difference between both ofthe additional data can be obtained by a simple logic circuit.

[0018] According to another aspect of the FIR filter of the presentinvention, the FIR filter includes the shift register, the factormultipliers, and switches. The shift register receives input data insequence and transmits the received input data to the delay elements.Each of the factor multipliers multiplies an output from each of thedelay elements of the shift register by tap factors. The switches areswitched on and off in response to a shift operation of the input datain the shift register and transmit outputs from the factor multipliersto the first operational unit or the second operational unit.

[0019] A bit width of the input data can be shortened, thereby reducingthe number of the factor multipliers and the circuit scale of the firstoperational unit or the second operational unit.

[0020] According to another aspect of the FIR filter of the presentinvention, the FIR filter includes the holding circuit and anoperational circuit. The holding circuit accepts the additional data inresponse to a change in input data and holds the accepted data as theadditional data corresponding to previous data. The operational circuitobtains a ratio of the additional data outputted from the holding datato new additional data. Thereby, the ratio of both of the additionaldata can be obtained by a simple logic circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The nature, principle, and utility of the invention will becomemore apparent from the following detailed description when read inconjunction with the accompanying drawings in which like parts aredesignated by identical reference numbers, in which:

[0022]FIG. 1 is a block diagram showing a first embodiment of thepresent invention;

[0023]FIG. 2 is a block diagram showing an FIR filter in FIG. 1 indetail;

[0024]FIG. 3 is an explanatory chart showing data inputted to an addertree ADT2;

[0025]FIG. 4 is an explanatory chart showing an operation of the FIRfilter in FIG. 1;

[0026]FIG. 5 is a block diagram showing an FIR filter according to asecond embodiment of the present invention;

[0027]FIG. 6 is a block diagram showing an FIR filter according to athird embodiment of the present invention;

[0028]FIG. 7 is an explanatory chart showing data inputted to an adderADD4;

[0029]FIG. 8 is a block diagram showing an FIR filter according to afourth embodiment of the present invention;

[0030]FIG. 9 is an explanatory chart showing data inputted to an addertree ADT2;

[0031]FIG. 10 is an explanatory chart showing an operation of the FIRfilter in FIG. 8;

[0032]FIG. 11 is a block diagram showing an FIR filter according to afifth embodiment of the present invention;

[0033]FIG. 12 is an explanatory chart showing an operation of the FIRfilter in FIG. 11; and

[0034]FIG. 13 is a block diagram showing an FIR filter according to asixth embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] Hereinafter, embodiments of the present invention is describedwith reference to the drawings.

[0036]FIG. 1 shows a first embodiment of an FIR filter, a method ofoperating the FIR filter, a semiconductor integrated circuit includingthe FIR filter, and a communication system for transmitting datafiltered by the FIR filter of the present invention.

[0037] The FIR filter 2 is used in a transmission circuit 6 of aportable terminal 4 in a communication system of, for example, a CDMAsystem or a W-CDMA (Wideband-CDMA) system. The transmission circuit 6with CMOS transistors and so on integrated is formed as a single chip ona Si substrate by utilizing semiconductor manufacturing technology. Asignal transmitted from the portable terminal 4 is received in a basestation 8.

[0038]FIG. 2 shows the FIR filter 2 in detail.

[0039] The FIR filter 2 has a shift register 10, factor multipliersMLT1, MLT2, MLT3, MLT4, a first operational unit 12, a secondoperational unit 14, an adder ADD6, and switches SW1, SW2, SW3.

[0040] The shift register 10 is composed of flip-flops FF1, FF2, FF3,FF4 (delay elements) connected in series for holding input data DIN. Inthis embodiment, a bit width of the input data DIN is set at, forexample, 5 bits. Therefore, the shift register 10 receives the inputdata DIN of 5 bits on the initial flip-flop FF1 and then sequentiallyshifts the received data to the subsequent flip-flops FF2 to FF4 insynchronization with a sampling trigger signal (not shown). The factormultipliers MLT1 to MLT4 respectively multiply output data from theflip-flops FF1 to FF4 by tap factors C1 to C4.

[0041] The first operational unit 12 includes an adder tree ADT1composed of adders ADD1, ADD2, ADD3, and a multiplier MLT4. The addertree ADT1 adds data outputted from the factor multipliers MLT1 to MLT4to output the addition result to the multiplier MLT5. The multiplier MLT5 multiplies the addition result by additional data. Here, theadditional data is information which is added in order to transmit theinput data DIN to a receiving side (the base station 8 in this case)without fail. In this embodiment, the additional data varies, forexample, according to a change in a transmission rate of the data. Themaximum bit width (a resolving power) of the additional data is set at 7bits.

[0042] The second operational unit 14 includes an adder tree ADT2composed of adders ADD4, ADD5, and a factor multiplier MLT6. The addertree ADT2 receives data outputted from the factor multipliers MLT2 toMLT4 via the switches SW1 to SW3 to output the addition result to amultiplier 6. The switches SW1 to SW3 are composed, for example, of CMOStransmission gates. The multiplier MLT6 multiplies the addition resultby a difference in additional data. Here, the difference in additionaldata means a difference between additional data corresponding toprevious data and additional data corresponding to present input data.

[0043] The adder ADD6 adds data outputted from the multipliers MLT5,MLT6 to output the addition result as output data DOUT (a filterresponse).

[0044] In this embodiment, as a way of example and for simpleexplanation, the filter is composed of four flip-flops FF1 to FF4,multipliers corresponding to the flip-flops FF1 to FF4, and adders. Inan actual FIR filter, the number of flip-flops (a bit length of inputdata) and circuit scales of adder trees and so on are larger than thoseof the flip-flops in FIG. 2.

[0045]FIG. 3 shows data inputted to the adder tree ADT2 in FIG. 2.

[0046] In the drawing, data A, B, C, and D are previous data held in theflip-flops FF1 to FF4 of the shift register 10, and data a, b, c, and dare newly inputted to the shift register 10 (present data). The arrowindicates a shift direction of the data.

[0047] At a time Dt−1, the flip-flops FF1 to FF4 hold the previous dataD, C, B, and A respectively. At this time, the switches SW1 to SW3 areoff.

[0048] At a time Dt, the shift register 10 performs a shift operationand the flip-flops FF2 to FF4 hold the data D, C, and B, respectively.The initial flip-flop FF1 holds data (present data) newly inputted tothe filter. At this time, the switches SW1 to SW3 are on. Therefore, theadder tree ADT2 receives the previous data B, C, and D, and then addsthe received data.

[0049] At a time Dt+1, the shift register 10 performs a shift operationand the flip-flops FF1 to FF4 hold the present data b, a and theprevious data D, C, respectively. At this time, the switch SW1 is off.Zero is supplied to a terminal of the adder tree ADT2 corresponding tothe switch in an off-state. Therefore, the adder tree ADT2 receives theprevious data C, D and adds the received data.

[0050] At a time Dt+2, the shift register 10 performs a shift operationand the flip-flops FF1 to FF4 hold the present data c, b, a, and theprevious data D, respectively. At this time, the switch SW2 is off.Therefore, the adder tree ADT2 receives only the previous data D to beoutput to the multiplier MLT6.

[0051] At a time Dt+3, the shift register 10 performs a shift operationand the flip-flops FF1 to FF4 hold the present data d, c, b, and a,respectively. At this time, the switch SW 3 is off. Therefore, the newdata d, c, b, and a are not transmitted to the adder tree ADT2.

[0052] In this way, the adder tree ADT2 operates as an operationalcircuit for constantly adding previous data.

[0053]FIG. 4 shows an operation of the FIR filter when the additionaldata (transmission rate) changes (at the time Dt in FIG. 3).

[0054] The time when the data is supplied to the filter is shown in thehorizontal direction of the drawing. In other words, the flip-flops FF1to FF4 holding the data are shown. In the vertical direction of thedrawing shown is the transmission rate (resolving power). In thisexample, a case where the transmission rate is altered from “6” (“000 011 0” in binary number) to “2” (“000 0010” in binary number). This meansthat the previous data (D, C, B, and so on) are transmitted at thetransmission rate “6” and the present data (a and so on) are transmittedat the transmission rate “2”. In the FIR filter 2, a region surroundedby the bold line is required to be an output response.

[0055] The second operational unit 14 in FIG. 2 multiplies the previousdata D, C, and B by a difference in the transmission rate (in this case,“4”, which is a difference between the transmission rate “6” and thetransmission rate “2”) in the multiplier MLT6. The multiplication resultcorresponds to the upper frame depicted with a broken line in FIG. 4.The first operational unit 12 in FIG. 2 multiplies the present data “a”and the previous data D, C, and B by the present transmission rate “2”in the multiplier MLT5. The multiplication result corresponds to thelower frame depicted with a broken line in FIG. 4. Then, themultiplication results are added in the adder ADD6 in FIG. 2 to generateoutput data DOUT (an output response) corresponding to a regionsurrounded by the frame depicted with a bold line in the drawing.

[0056] In this embodiment described above, the input data and theadditional data are separately received to be operated and then theoutput data DOUT is generated. Therefore, the circuit scale of thefilter can be reduced compared with a case where data which is inputdata and additional data combined and has a large bit width, isreceived. In other words, the bit width of the input data DIN inputtedto the shift register 10 can be decreased so that the number of thefactor multipliers can be decreased, and thereby circuit scales of theadder trees 12, 14 and the multipliers MLT5, MLT 6 can be reduced.Therefore, a chip of the semiconductor integrated circuit can bedownsized to realize cost reduction of the communication system.

[0057] Particularly, a remarkable effect can be obtained by separatelyreceiving the input data DIN and the additional data such as thetransmission rate which changes only in a long cycle.

[0058] The switches SW1 to SW3 are formed and switched off in responseto every shift operation of the shift register 10. The switching-off isperformed in sequence starting from the switch corresponding to thefactor multiplier on an input side. Consequently, only the previous dataamong the data supplied to the shift register 10 can be transmitted tothe adder tree 14 without fail.

[0059]FIG. 5 shows an FIR filter according to a second embodiment of thepresent invention. The same symbols and numerals are added to the samecircuits and signals as those described in the first embodiment and thedetailed explanation thereof is omitted.

[0060] As in the first embodiment, the FIR filter is used in atransmission circuit (a semiconductor integrated circuit) of a portableterminal in a communication system of, for example, a CDMA system or aW-CDMA (a Wideband-CDMA) system. The FIR filter according to thisembodiment is constituted with a holding circuit 16 and an operationalcircuit 18 additionally provided in the FIR filter 2 in FIG. 2. Otherstructures are the same as those in the first embodiment (FIG. 2).

[0061] The holding circuit 16, which is composed of a flip-flop, acceptsadditional data (a transmission rate) in synchronization with a triggersignal TG which is generated every time input data DIN is supplied. As aresult, previous additional data is outputted from the holding circuit16. The operational circuit 18 obtains a difference between presentadditional data and the previous additional data held in the holdingcircuit 16 and outputs the obtained difference to the multiplier MLT6.

[0062] An operation of the FIR filter according to this embodiment isthe same as that in the first embodiment described above and therefore,the explanation thereof is omitted.

[0063] In this embodiment, the same effect is also obtained as in thefirst embodiment described above. In this embodiment, the difference inadditional data can be further obtained by simple logic circuits (theholding circuit 16 and the operational circuit 18). In other words, theoperation for obtaining the difference in additional data can be easilycontrolled.

[0064]FIG. 6 shows an FIR filter according to a third embodiment. Thesame symbols and numerals are added to the same circuits and signals asthose described in the first embodiment and the detailed explanationthereof is omitted.

[0065] As in the first embodiment, the FIR filter is used in atransmission circuit (a semiconductor integrated circuit) of a portableterminal in a communication system of, for example, a CDMA system or aW-CDMA (a Wideband-CDMA) system.

[0066] In this embodiment, a second operational unit 20 is formedinstead of the second operational unit 14 of the FIR filter 2 in FIG. 2and a shift switch SW4 is formed instead of the switch SW3. Otherstructures are the same as those in the first embodiment (FIG. 2).

[0067] The second operational unit 20 includes an adderADD4 and amultiplier MLT6. The switch SW1 transmits data outputted from the factormultiplier MLT2 to the adder ADD 4. The switch SW2 transmits dataoutputted from the adder ADD2 of the adder tree ADT1 to the adder ADD4via the shift switch SW4. The shift switch SW4 transmits either theoutput data from the adder ADD2 or output data from the factormultiplier MLT4 to the adder ADD4.

[0068]FIG. 7 shows data inputted to the second operational unit 20 inFIG. 6. The explanation on the same operations as those in FIG. 3described above is omitted. “L” in the drawing indicates that the shiftswitch SW4 is connected to the switch SW2 and “R” indicates that theshift switch SW4 is connected to the factor multiplier MLT4.

[0069] At a time Dt−1, the switches SW1, SW2 are off and the shiftswitch SW4 is connected to the switch SW2. At a time Dt, the switchesSW1, SW2 are on and the adderADD4 receives previous data B, C, and D. Ata time Dt+1, the switch SW1 is off and the adder ADD4 receives theprevious data C and D. At a time Dt+2, the switch SW2 is off and theshift switch SW4 is connected to the factor multiplier MLT4. As aresult, the adder ADD4 receives only the previous data D and outputs itto the multiplier MLT6. At a time Dt+3, the switches SW1, SW2 are offand the shift switch SW4 is connected to the switch SW2. As a result,new data d, c, b, and a are not transmitted to the adder ADD4. In thisway, the adder ADD4 operates as an operational circuit for constantlyadding previous data.

[0070] An operation of the FIR filter according to this embodiment isthe same as that in the first embodiment described above and therefore,the explanation thereof is omitted. In this embodiment, the same effectis also obtained as in the first embodiment described above.Furthermore, the addition result from the adder ADD2 in the adder treeADT1 is utilized as data for the addition in the second operational unit20 in this embodiment. Consequently, a circuit scale of the secondoperational unit 20 can be reduced.

[0071]FIG. 8 shows an FIR filter according to a fourth embodiment of thepresent invention. The same symbols and numerals are added to the samecircuits and signals as those described in the first embodiment and thedetailed explanation thereof is omitted.

[0072] As in the first embodiment, the FIR filter is used in atransmission circuit (a semiconductor integrated circuit) of a portableterminal in a communication system of, for example, a CDMA system or aW-CDMA (Wideband-CDMA) system.

[0073] In this embodiment, shift switches SW5, SW6, and SW7 are formedinstead of the switches SW1 to SW3 in the first embodiment. The switchesSW5 to SW7 transmit the data outputted from the respective factormultipliers MLT2 to MLT4 to either the adder tree ADT1 or the adder treeADT2. The multiplier MLT5 of the first operational unit 12 receivespresent additional data (a transmission rate) and the multiplier MLT6 ofthe second operational unit 14 receives previous additional data (atransmission rate). Other structures are the same as in the firstembodiment (FIG. 2).

[0074]FIG. 9 shows data inputted to the first operational unit 12 andthe second operational unit 14 in FIG. 8. The explanation on the sameoperations as in FIG. 3 described above is omitted. “L” in the drawingindicates that the switches SW5 to SW7 are connected to the firstoperational unit 12 and “R” indicates that the shift switches SW5 to SW7are connected to the second operational unit 14.

[0075] At a time Dt−1, the shift switches SW5 to SW7 are connected tothe first operational unit 12. At this time, the output data from thefactor multipliers MLT2 to MLT4 are transmitted to the first operationalunit 12. At a time Dt, the shift switches SW5 to SW7 are connected tothe first operational unit 14. The first operational unit 12 receivespresent data “a” and the second operational unit 14 receives previousdata B, C, and D.

[0076] At a time Dt+1, the shift switch SW5 is connected to the firstoperational unit 12. The first operational unit 12 receives the presentdata a and b and the second operational unit 14 receives the previousdata C and D. At a time Dt+2, the shift switch SW6 is connected to thefirst operational unit 12. The first operational unit 12 receives thepresent data a, b, and c and the second operational unit 14 receivesonly the previous data D. At a time Dt+3, the shift switches SW5 to SW7are connected to the first operational unit 12. The output data from thefactor multipliers are transmitted to the first operational unit 12.

[0077] In this embodiment, the first operational unit 12 receives onlythe present data and the second operational unit 14 receives only theprevious data.

[0078]FIG. 10 shows an operation of the FIR filter when the transmissionrate is switched (at the time Dt in FIG. 9). The explanation on the sameoperations as in FIG. 4 described above is omitted.

[0079] The second operational unit 14 in FIG. 8 multiplies the previousdata D, C, and B by the previous transmission rate “6” in the factormultiplier MLT6. The multiplication result corresponds to the rightframe in FIG. 10 depicted with a broken line. The first operational unit12 in FIG. 8 multiplies the present data “a” by the present transmissionrate “2” in the multiplier MLT5. The multiplication result correspondsto the left frame depicted with a broken line in FIG. 10. The adder ADD6in FIG. 8 then adds the multiplication results to generate output dataDOUT which corresponds to a region surrounded by the frame depicted witha bold line in FIG. 10.

[0080] In this embodiment, the same effect is also obtained as in thefirst embodiment 10 described above.

[0081]FIG. 11 shows an FIR filter according to a fifth embodiment of thepresent invention.

[0082] The same symbols and numerals are added to the same circuits andsignals as those described in the first and the fourth embodiments andthe detailed explanation thereof is omitted.

[0083] As in the first embodiment, the FIR filter is used in atransmission circuit (a semiconductor integrated circuit) of a portableterminal in a communication system of, for example, a CDMA system or aW-CDMA (Wideband-CDMA) system.

[0084] In this embodiment, a first operational unit 22 is formed insteadof the first operational unit 12 of the FIR filter shown in FIG. 8. Inaddition, a multiplier MLT7 for receiving an output from the adder ADD6is newly formed. The multiplier MLT6 of the second operational unit 14receives a ratio of additional data (a transmission rate) correspondingto previous data to additional data corresponding to present data (adenominator is the present additional data). Other structures are thesame as those in the fourth embodiment (FIG. 8).

[0085] The first operational unit 22 is composed of the same adder treeADT1 as that in FIG. 8. The adder ADD6 multiplies data outputted fromthe adder tree ADT1 by data outputted from the multiplier MLT6 of thesecond operational unit 14 and outputs the multiplication result to themultiplier MLT7. The multiplier MLT7 multiplies data from the adder ADD6by the present additional data (transmission rate) and outputs themultiplication result as output data DOUT (an output response).

[0086]FIG. 12 shows an operation of the FIR filter when a transmissionrate is changed. The explanation on the same operations as those in FIG.4 is omitted. In this example, the ratio of the transmission rates,which equals to (the previous transmission rate “6”)/(the presenttransmission rate “2), is set at “3”.

[0087] The multiplier MLT6 of the second operational unit 14 in FIG. 11multiplies the previous data D, C, and B by a ratio of transmissionrates “3”. The multiplication result corresponds to the right framedepicted with a broken line in FIG. 12. The multiplier MLT5 of the firstoperational unit 22 in FIG. 11 receives present data a and outputs thereceived data to the adder ADD6 (corresponding to the left framedepicted with a broken line in FIG. 12). These data are added in theadder ADD6 and transmitted to the multiplier MLT7. The multiplier MLT7then multiplies the data from the adder ADD6 by the present transmissionrate “2”. The multiplication result corresponds to the frame depictedwith a bold line in the drawing, which is “twice” as large as the twoframes depicted with a broken line.

[0088] In this embodiment, the same effect is also obtained as in thefirst embodiment described above.

[0089]FIG. 13 shows an FIR filter according to a sixth embodiment of thepresent invention. The same symbols and numerals are added to the samecircuits and signals as those described in the first embodiment and thedetailed explanation thereof is omitted.

[0090] As in the first embodiment, the FIR filter is used in atransmission circuit (a semiconductor integrated circuit) of a portableterminal in a communication system of, for example, a CDMA system or aW-CDMA (Wideband-CDMA) system. The FIR filter according to thisembodiment is constituted with the holding circuit 16 and an operationalcircuit 24 additionally provided in the FIR filter 2 in FIG. 11. Otherstructures are the same as those in the sixth embodiment (FIG. 11).

[0091] The holding circuit 16, which is composed of a flip-flop, acceptsadditional data (a transmission rate) in synchronization with a triggersignal TG which is generated every time input data DIN is supplied. As aresult, previous additional data is outputted from the holding circuit16. The operational circuit 24 obtains a ratio of present additionaldata to the previous additional data held by the holding circuit 16 andthen outputs the obtained ratio to the multiplier MLT6.

[0092] An operation of the FIR filter according to this embodiment isthe same as that in the first embodiment described above and therefore,the explanation thereof is omitted.

[0093] The same effect is also obtained as in the second and the sixthembodiments described above. In this embodiment, the ratio of theadditional data can be further obtained by simple logic circuits (theholding circuit 16 and the operational circuit 24). In other words, theoperation for obtaining the ratio of the additional data can be easilycontrolled.

[0094] Incidentally, in the above embodiments there have been describedexamples where the input data DIN consisting of transmitting informationand additional data (for example, a transmission rate) which is added inorder to transmit the input data DIN are separately received to generatethe output data DOUT. However, the present invention is not limited tothe above embodiments. For example, data including the input data DINand the additional data may be received and standardized in a dataseparation unit provided in the FIR filter, and the standardized data isseparated into the input data DIN and the additional data so as togenerate output data from the separated data.

[0095] Furthermore, the additional data does not have to be atransmission rate. The additional data may be any data as long as it isadded to the input data DIN for the purpose of reliably receiving theinput data DIN consisting of transmitting information at a transmissionside.

[0096] The invention is not limited to the above embodiments and variousmodifications may be made without departing from the spirit and thescope of the invention. Any improvement may be made in part or all ofthe components.

What is claimed is:
 1. An FIR filter comprising: a first operationalunit for operating input data which consists of transmitting informationand is composed of bit strings, and additional data which is added inorder to transmit said input data and; a second operational unit foroperating previous data among said input data and a difference betweensaid additional data corresponding to the previous data and saidadditional data corresponding to present data among said input data; andan adding unit for adding results of the first and second operations andoutputting the resultant as a filter response.
 2. The FIR filteraccording to claim 1, further comprising a data separation unit forseparating data inputted to the filter into said input data and saidadditional data.
 3. The FIR filter according to claim 1, furthercomprising: a shift register for receiving said input data in sequence;and factor multipliers for multiplying outputs from each of delayelements of said shift register by tap factors, and wherein: said firstoperational unit includes a first adder tree for adding outputs fromsaid factor multipliers and a first multiplier for multiplying an outputfrom said first adder tree by said additional data; said secondoperational unit includes a second adder tree for adding said previousdata among said outputs from said factor multipliers and a secondmultiplier for multiplying an output from said second adder tree by saiddifference; and said adding unit adds an output from said firstmultiplier and an output from said second multiplier.
 4. The FIR filteraccording to claim 3, further comprising switches for connecting outputsof said factor multipliers to said second adder tree, wherein saidswitches are switched on and off in response to a shift operation ofsaid input data in said shift register and transmit said previous datato said second adder tree.
 5. The FIR filter according to claim 4,wherein said switches are switched off in response to every shiftoperation of said shift register, the switching-off being performed insequence, starting from a switch corresponding to one of said factormultipliers at an input side.
 6. The FIR filter according to claim 3,further comprising switches for connecting said second adder tree to oneof an output of a predetermined one of said factor multipliers and anoutput of a predetermined one of adders which compose said first addertree, wherein said switches are switched on and off in response to ashift operation of said input data in said shift register and transmitsaid previous data to said second adder tree.
 7. The FIR filteraccording to claim 1, further comprising: a holding circuit foraccepting said additional data in response to a change in said inputdata and holding the accepted data as said additional data correspondingto said previous data; and an operational circuit for operating adifference between said additional data outputted from said holdingcircuit and new additional data.
 8. An FIR filter comprising: a firstoperational unit for operating present data among input data whichconsists of transmitting information and is composed of bit strings, andadditional data which is added in order to transmit said present data; asecond operational unit for operating previous data among said inputdata and said additional data corresponding to said previous data; andan adding unit for adding results of the first and second operations andoutputting the resultant as a filter response.
 9. The FIR filteraccording to claim 8, further comprising a data separation unit forseparating data inputted to the filter into said input data and saidadditional data.
 10. The FIR filter according to claim 8, furthercomprising: a shift register for receiving said input data in sequence;factor multipliers for multiplying outputs from each of delay elementsof said shift register by tap factors; and switches being switched onand off in response to a shift operation of said input data in saidshift register, for transmitting outputs from said factor multipliers toone of said first operational unit and said second operational unit. 11.An FIR filter comprising: a first operational unit for adding presentdata among input data which consists of transmitting information and iscomposed of bit strings; a second operational unit for operatingprevious data among said input data and a ratio of said additional datacorresponding to said previous data to said additional datacorresponding to said present data; an adding unit for adding an outputfrom said first operational unit and an output from said secondoperational unit; and a multiplying unit for multiplying an output fromsaid adding unit by said additional data corresponding to said presentdata and for outputting the resultant as a filter response.
 12. The FIRfilter according to claim 11, further comprising a data separation unitfor separating data inputted to the filter into said input data and saidadditional data.
 13. The FIR filter according to claim 11, furthercomprising: a shift register for receiving said input data in sequence;factor multipliers for multiplying outputs from each of delay elementsof said shift register by tap factors; and switches being switched onand off in response to a shift operation of said input data in saidshift register, for transmitting outputs from said factor multipliers toone of said first operational unit and said second operational unit. 14.The FIR filter according to claim 11, further comprising: a holdingcircuit for accepting said additional data in response to a change insaid input data and holding the accepted data as said additional datacorresponding to said previous data; and an operational circuit foroperating a ratio of said additional data outputted from said holdingcircuit to new additional data.
 15. A method of operating an FIR filter,comprising the steps of: receiving in sequence input data which consistsof transmitting information and is composed of bit strings; operatingsaid input data and additional data which is added in order to transmitsaid input data; operating previous data among said input data and adifference between said additional data corresponding to said previousdata and said additional data corresponding to present data; and addingresults of said operations and outputting the resultant as a filterresponse.
 16. A method of operating an FIR filter, comprising the stepsof: receiving in sequence input data which consists of transmittinginformation and is composed of bit strings; operating present data amongsaid input data and additional data which is added in order to transmitsaid present data; operating previous data among said input data andsaid additional data corresponding to said previous data; and addingresults of said operations and outputting the resultant as a filterresponse.
 17. A method of operating an FIR filter, comprising the stepsof: receiving in sequence input data which consists of transmittinginformation and is composed of bit strings and; adding present dataamong said input data; operating previous data among said input data anda ratio of said additional data corresponding to said previous data tosaid additional data corresponding to said present data; adding resultsof said operations; multiplying the addition result by said additionaldata corresponding to said present data; and outputting themultiplication result as a filter response.
 18. A semiconductorintegrated circuit including an FIR filter, wherein the FIR filtercomprises: a first operational unit for operating input data whichconsists of transmitting information and is composed of bit strings, andadditional data which is added in order to transmit said input data; asecond operational unit for operating previous data among said inputdata and a difference between said additional data corresponding to theprevious data and said additional data corresponding to present dataamong said input data; and an adding unit for adding results of thefirst and second operations and outputting the resultant as a filterresponse.
 19. A semiconductor integrated circuit including an FIRfilter, wherein the FIR filter comprises: a first operational unit foroperating present data among input data which consists of transmittinginformation and is composed of bit strings, and additional data which isadded in order to transmit said present data; a second operational unitfor operating previous data among said input data and said additionaldata corresponding to said previous data; and an adding unit for addingresults of the first and second operations and outputting the resultantas a filter response.
 20. A semiconductor integrated circuit includingan FIR filter, wherein the FIR filter comprises: a first operationalunit for adding additional data corresponding to present data amonginput data which consists of transmitting information and is composed ofbit strings; a second operational unit for operating previous data amongsaid input data and a ratio of said additional data corresponding tosaid previous data to said additional data corresponding to said presentdata; an adding unit for adding an output from said first operationalunit and an output from said second operational unit; and a multiplyingunit for multiplying an output from said adding unit by said additionaldata corresponding to said present data and for outputting the resultantas a filter response.
 21. A communication system for transmitting datafiltered by an FIR filter, the communication system comprising: a firstoperational unit for operating input data which consists of transmittinginformation and is composed of bit strings, and additional data which isadded in order to transmit said input data; a second operational unitfor operating previous data among said input data and a differencebetween said additional data corresponding to the previous data and saidadditional data corresponding to present data among said input data; andan adding unit for adding results of the first and second operations andoutputting the resultant as a filter response.
 22. A communicationsystem for transmitting data filtered by an FIR filter, thecommunication system comprising: a first operational unit for operatingpresent data among input data which consists of transmitting informationand is composed of bit strings, and additional data which is added inorder to transmit said present data; a second operational unit foroperating previous data among said input data and said additional datacorresponding to said previous data; and an adding unit for addingresults of said first and second operations and outputting the resultantas a filter response.
 23. A communication system for transmitting datafiltered by an FIR filter, the communication system comprising: a firstoperational unit for adding present data among input data which consistsof transmitting information and is composed of bit strings; a secondoperational unit for operating previous data among said input data and aratio of said additional data corresponding to said previous data tosaid additional data corresponding to said present data; an adding unitfor adding an output from said first operational unit and an output fromsaid second operational unit; and a multiplying unit for multiplying anoutput from said adding unit by said additional data corresponding tosaid present data and for outputting the resultant as a filter response.